by Dr Tony Curzon Price, 1/28/2005
Wireless Design & Development, February 2005 issue
Emerging wireless standards such as 801.11n mandate over-the-air throughput of 200+ Mb/s. This five- to ten-fold increase over the 802.11a standard is creating a daunting challenge for next generation wireless hardware design and development. Designers typically focus their efforts on optimizing IC designs to meet these increased system-level performance requirements. However, the brute force approach of simply migrating existing IC designs to smaller and smaller manufacturing process geometries is no longer viable; due to the law of diminishing returns, crude replication of faster hardware does not deliver the required throughput. And to make matters worse, product cost increases exponentially with the migration to smaller IC process geometries, while power savings are mitigated by the increased clock frequencies used at these geometries. A completely new approach to wireless system-level design is necessary to successfully meet the performance, power, and cost requirements of today's products and to provide adequate headroom for tomorrow's products.
This article is available as a pdf (800Kb). Download it here.
Sidebar written by Chris Dick of Xilinx
Dr. Chris Dick is the Director of Signal Processing Systems Engineering at Xilinx, Inc. He is responsible for coordinating the DSP intellectual property engineering activities and is the DSP Chief Architect at Xilinx with research interests in the area of software defined radio and real time digital signal processing. He joined Xilinx in 1997 from La Trobe University in Melbourne, Australia where he was a professor for 13 years. Dick holds bachelor's and Ph.D. degrees in computer science and electronic engineering.
