By Peter Clarke, EE Times, 4/1/2004
London - A company that claimed it could improve silicon performance and reduce die area with its innovations in mathematical circuit blocks has launched a set of logic cell libraries that make those approaches available for custom and standard-cell design.
Arithmatica Inc. is licensing approaches it first touted in July 2002, when the company was called Automatic Parallel Designs Ltd. At the time AutoPD claimed it could increase processor performance while saving die area and power simply by a redesign of the basic multiplier and adder circuitry that is at the heart of math and logic functions. (View article)
Those claims have now been fleshed out with reference to the 0.13-micron low-voltage CMOS manufacturing process from foundry Taiwan Semiconductor Manufacturing Co. Ltd. Comparisons were made with the results achievable using an automated cell-based design flow and standard cells from Artisan Components Inc.
Arithmatica's proposition is based on faster methods to generate carries in integer adders and on faster parallel counters for multiplication and other functions. The company two years ago claimed that a 20 percent performance gain, 30 percent area reduction and reduced pipeline stages were achievable, without changing processor architecture, design method or manufacturing process.
Performance gains are said to accrue both at the cell level and at the architectural level-in the pervasive arithmetic functions, such as adders and multipliers, along with architectural optimizations that further improve such tasks as floating-point math, single-instruction multiple-data instruction execution and exponentiation performance.
The company has applied for 15 patents covering fundamental logic improvements to a broad range of arithmetic operations. Arithmatica's R&D facility in Warwick, England, is claimed to be one of the largest dedicated silicon math research groups in the industry.
Arithmatica says its innovations have attracted numerous licensees, including two multibillion-dollar semiconductor companies. Standard-cell users can license configurable math instances or applications libraries that contain the functions commonly used to implement advanced graphics or DSP designs. The custom market is served through licensing of the core silicon arithmetic technology. Licenses are issued either per design, with fees varying according to the intellectual property used, or on an annual-subscription basis.
AutoPD was founded in Oxford, England, in 1998 by mathematician Sunil Talwar and game theorist Tony Curzon Price, who sought to exploit UK university research on efficient state encoding. Curzon Price now serves Arithmatica - which relocated its headquarters to Redwood City, Calif. - as chief operating officer, and Talwar is chief technology officer. David Burow, former general manager of the High Level Verification Group at Synopsys Inc., is CEO.
In March 2001, AutoPD received $2.5 million from venture capital firm Quester, plus a further $550,000 from a group of investors. In August, as Arithmatica, the company undertook a second round.
