Join us for an educational and free webinar on innovative design techniques for reducing power consumption in datapath design. A CellMath IP case study will be presented that illustrates design tradeoffs and synthesis techniques for minimizing power consumption. Attendees will gain insight into how key architectural, design, and implementation decisions were made to significantly reduce power and area.
Date: May 6, 2008
Time: 5:00 PM UK, 9:00 AM Pacific
Registration: https://cc.readytalk.com/registration/1qntjqvpk9cef/1q0bgedujg8sl
Agenda
Introduction
Designing for Low-Power
CellMathIP Case Study:
3D Floating Point Vector Normalizer
Architecture definition: Design decisions and tradeoffs
Functional design: Verilog model using default floating point operators
Implementation: Gate-level creation using datapath synthesis
Design optimizations: Customization of floating point operators
Power saving techniques: Integrated register stalling management
PRESENTER
Peter Meulemans
Director of Consulting and Design Services, Arithmatica
Peter started at Arithmatica in 1999 while working on his PhD in digital signal and image processing at the University of Warwick, UK. After receiving his PhD in 2001, Peter joined Arithmatica as a full time member and was integral in the R&D of Arithmatica's core technical innovations. Peter has extensive expertise in datapath design, ASIC synthesis, and formal verification techniques.
