Join us for an informative and educational free webinar on datapath design optimization. Arithmatica's top mathematicians and design engineers, along with an expert industry guest speaker, will discuss and demonstrate techniques for reducing power, minimizing area, and increasing performance of datapath designs.
Date: January 29, 2008
Time: 5:00 PM UK, 9:00 AM Pacific
Registration:
Agenda
Opening Remarks
Michael Bohm
RTL Coding Styles for Datapath Synthesis
Matt Probert, Senior Engineer
What's New in Datapath Synthesis
Nick Atkinson, Vice President of Product Development
Optimizing Datapaths for Power
Robert Jackson, Senior Engineer
Roundtable Discussion/Q&A
Arithmatica Speakers
Nick Atkinson
Vice President of Product Development
Nick joined Arithmatica in 2002 after achieving a first class degree in computer science at the University of Warwick, UK. Nick joined Arithmatica as a Member of Technical Staff and worked in both the design services team and the software development team before taking the position of Vice President of Product Development, where he has managed the development, launch and support of Arithmatica's CellMath suite of tools and IP.
Matt Probert
Senior Engineer
Robert Jackson
Senior Engineer
Matt and Robert are senior members of Arithmatica's technical staff responsible for outsourced datapath design services, product innovation, and design flow/consulting services. They have worked on numerous customer IC design projects providing expert advice and design knowledge to produce cooler, smaller, and faster datapath modules.
Guest Speaker
Michael Bohm
Consultant
Michael was previously the CTO of AccelChip and of the synthesis group at Mentor Graphics, and held the VP of Engineering position at Exemplar Logic. An IC design engineer/manager by trade, Michael started his career at Harris Semiconductor where he led the development of many digital and mixed signal ICs. Currently the Principal of his own consulting company, Michael is considered one of the industry's leading technical experts in synthesis, FPGA, and ASIC technologies.
