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Teranetics is a leading mixed-signal IC company that develops silicon
products for the most advanced communication applications. 10GBASE-T (10
Gigabit Ethernet over copper) chips represent some of the most
sophisticated mixed signal designs in existence. The challenge of error
correction over copper at these data rates requires very high
performance signal processing and all of this has to be achieved within
a power envelope that does not compromise system reliability or
robustness.
Teranetics selected CellMath Designer to complement their existing IC
design flow to provide the datapath-specific optimization capabilities
required to meet their power consumption, performance and area
utilization goals. CellMath Designer also produced simulation and formal
verification models that significantly reduce the verification time
required.
The development of 10GBASE-T arguably represents the most significant
technological development for Ethernet this decade. The power, speed and
capacity of 10GBASE-T over traditional copper media opens new avenues
for networking products designed to deliver on the promise of BASE-T
connectivity for a new generation of high bandwidth/high capacity
applications. As a leading provider of high-performance, mixed-signal
digital semiconductors, Teranetics has introduced the industry's first
single-chip implementation of 10GBASE-T. The TN1010 represents the state
of the art in communication system theory and mixed-signal technology.
"The winners in the 10GBASE-T market will be defined by the highest
performance and most power efficient designs. CellMath Designer enabled
our team to significantly reduce overall chip power and reduce datapath
area while meeting the throughput requirements in our critical signal
processing blocks. In addition, the behavioral models provide an elegant
way to formally verify the netlist, easing the verification bottleneck
typical in complex signal processing designs."
-- Sridhar Begur, Vice President, ASIC Engineering, Teranetics
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